Historically, most performance improvements in semiconductor field-effect transistors (FET) have been achieved by scaling down the relative dimensions of the device. This trend is becoming increasingly more difficult to maintain as the devices reach their physical scaling limits. As a consequence, advanced FETs and the complementary metal oxide semiconductor (CMOS) circuits in which they can be found are increasingly relying on strain engineering and specialty silicon-on-insulator substrates to achieve desired circuit performance.
One method of introducing compressive strain in a silicon channel region is to epitaxially grow a silicon-germanium (SiGe) material within recesses formed in the semiconductor body. The silicon germanium atom has a different lattice spacing than the silicon atom thereby imparting a compressive strain to the channel region under the gate. This is referred to as an embedded SiGe process.
Improved performance in transistors fabricated using an embedded SiGe process is desired.